The present invention relates to a mounting structure for an integrated circuit device and its mounting method, and more particularly, to a mounting structure for an integrated circuit device using a film carrier and its mounting method.
An example of conventional mounting structures for integrated circuit devices is disclosed in Japanese Patent Application Laid-open No. Hei 2-185051.
Referring to FIG. 5, in the conventional mounting structure such one as disclosed in the above reference, conductive wiring 500 comprises an inner lead 501 and an outer lead 502. The inner lead 501 is connected to an electrode pad of an IC chip. The outer lead 502 is connected to a connection pad provided on the substrate. The inner and outer leads 501 and 502 are electrically connected through the conductive wiring 500 on a film carrier 300 (hereinafter referred to as Reference 1).
In addition, TAB tape having two metal wiring layers is described in Shin Kayama and Kunihiko Naruse, "Practical Lecture: VLSI Packaging Technology (Vol. 2)", 1993, Nikkei BP, p.174 (hereinafter referred to as Reference 2).
In the Reference 1, the inner and outer leads are electrically connected through first wiring on a carrier film. Noise appears in signals transmitting through the first wiring on the carrier film since the first wiring is easily affected by noise generated by signals transmitting through second wiring on the substrate. This is because only the carrier film lies between the first and second wiring without having a ground layer. In addition, there is also a problem that characteristic impedance of the second wiring on the substrate cannot be matched with impedance from the inner lead to the outer lead.
On the other hand, it is contemplated to arrange one of two metal wiring layers as a ground layer by using the TAB tape described in the Reference 2. However, the complicated manufacturing method of TAB tape leads to another problem that the lead time for manufacturing becomes longer.